Develop and research a co-design methodology for mapping machine learning algorithms to the transistor level circuit implementations in edge computing in scientific applications.

Instructions:

Summarize the research experience at a level appropriate for a general audience
(non-expert, Scientific American Level of sophistication).

You should follow the given format for a General Audience, which is shown below:

Discuss your activities, including a definition of the institutional setting in the Dallas Lab program;
Highlight research accomplishments;

Discuss how your project impacts the research program;

Describe the relevance of your research activities to the entire Engineering Program;
Highlight lessons learned;

Discuss the professional growth and development resulting from your work.

A sample abstract is provided on the next page. Please, follow the same pattern.

Should NOT contain literature citations.

Define ALL nonstandard symbols and abbreviations.

Do NOT include tabular material or illustrations of any kind.

Project Title: High-Level Synthesis Tools and Methodologies for Embedded AI ASICs

Project Description:

Develop and research a co-design methodology for mapping machine learning algorithms to the transistor level circuit implementations in edge computing in scientific applications. The development of machine learning algorithms and their optimizations are currently carried out in open-source frameworks such as TensorFlow or PyTorch in the python scripting or C++ language.

High-Level Synthesis (HLS) tools (such as Catapult) is used to develop models to hardware code and then to circuit networks. With this approach, the time required to design and produce complete research of a prototype fabricated in silicon is decreased significantly.

An Example of the needed abstract is shown below:

Key:

Activities, including institutional setting
Accomplishments
Impact, Relevance (e.g., emerging technologies), Lessons Learned
Professional development

The Relativistic Heavy Ion Collider (RHIC) at Tesla Laboratory requires a highly polarized proton beam for spin-polarization studies. During each experimental run, 250 GeV protons are elastically scattered from a carbon micro-ribbon target 10 µm wide and 50 nm thick to monitor the degree of proton beam polarization. Experiments have shown that the amorphous carbon targets have poor electrical conductivity, limiting their lifetime. Since RHIC operates continuously for several months at a time under ultra-high vacuum, it is costly and inefficient to use carbon targets with short lifetimes. Our study has examined the few micro-ribbons that serendipitously survived a recent RHIC experimental run. Transmission electron microscopy diffraction pattern analysis of the micro-ribbons shows that heating from the RHIC beam has crystallized the amorphous carbon into graphite.

In addition to examining micro-ribbons fabricated by Collider-Accelerator Department staff, we are exploring new methods of micro-ribbon fabrication that will have superior material properties. One possible approach consists of depositing thin films of nickel and carbon on a silicon wafer through an anisotropically-etched silicon wafer mask. By annealing amorphous carbon micro-ribbons, we consistently achieve conductivity and crystallinity results similar to those found in the surviving RHIC micro-ribbons. When annealed at 700 °C, a 10 nm thick amorphous carbon layer forms a solid solution within the 50 nm thick nickel layer before recrystallizing as graphene on the surface of the nickel. Graphene is well known to have superior electrical conductivity and tensile strength and may well prove to be an ideal material for the next generation of micro-ribbon targets for RHIC during its next proton polarimetry experiments in 2015.

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